1. Technical Field
The invention relates generally to electronic circuits and devices, and more specifically, to electronic devices having delay elements.
2. Related Art
Conventional inverter-chain delay lines are used to establish timing relationships between signals on an integrated circuit. These inverter chains, while easy to design, are prone to wide variations in propagation delay due to parametric sensitivities. The parametric sensitivities may include, for example, changes in threshold voltages and gamas due to process tolerances and temperature variations of the inverters. Additionally, it is difficult to design an inverter-chain delay element with programmable delay increments that are of predictable time intervals. If an inverter-chain delay element does include programmable delay increments, it is difficult to preserve the accuracy of the delays and uniformity of the delay steps over process voltage and temperature.
In order to overcome some of the problems of conventional inverter-delay circuits, programmable delay circuits including capacitors and a selection of current sources have been designed. Some examples of these delay circuits are found in the following U.S. Patents: U.S. Pat. No. 5,841,296, xe2x80x9cProgrammable Delay Element,xe2x80x9d issued November 1998 to Churcher et al.; U.S. Pat. No. 5,650,739, xe2x80x9cProgrammable Delay Lines,xe2x80x9d issued July 1997 to Hui et al.; U.S. Pat. No. 5,081,380, xe2x80x9cTemperature Self-Compensated Time Delay Circuits,xe2x80x9d issued January 1992 to Chen; and U.S. Pat. No. 4,742,331, xe2x80x9cDigital-To-Digital Converter,xe2x80x9d issued May 1988 to Barrow et al.
Unfortunately, the delay elements in most of the aforementioned patents also contain resistors and other elements that are still temperature dependent. Although the temperature variation is compensated for in some circuits, the prediction of the temperature variation takes time, may not be precise, and the compensation circuitry requires more space. The discharge of the capacitance in other circuits is not precise and a programmable delay cannot be produced at predictable time intervals. Furthermore, because of the arrangement of the field-effect transistors (FETs) in some of the aforementioned patents, a certain amount of time is expended for the delay circuit to get out of an unpredictable region (the linear region) to a more predictable region (the saturation region), which ultimately degrades precision of the delay.
Accordingly, a need has developed in the art for a delay element that will not only quickly reach a linear and predictable state of operation, but is substantially resistant to parametric sensitivities.
It is thus an advantage of the present invention to provide a programmable delay element that is substantially independent of parametric sensitivities, such as temperature variations.
It is also an advantage of the present invention to provide a programmable delay element that will quickly reach a linear and predictable state of operation.
It is also an advantage of the present invention to provide a programmable delay pulse generator that is substantially immune to noise.
The foregoing and other advantages of the invention are realized by a programmable delay element having a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, wherein the delay of the delayed signal is defined by the programmable, predetermined amount of current.
Generally, the present invention provides a programmable delay device comprising:
a current source field-effect transistor (FET) for gating a predetermined amount of current;
a switch device, coupled to said current source FET, for receiving an input signal having a first and second voltage level; and
an inverter device, coupled to the drain of said current source FET, for outputting a delayed signal when said input signal is at said first voltage level, a delay of said delayed signal defined by said predetermined amount of current.
In addition, the present invention provides a method for delaying an input signal comprising the steps of:
a) precharging a capacitance node when an input signal is at a first voltage level;
b) discharging said capacitance node by gating a predetermined amount of current through a current source FET when said input signal is at a second voltage level;
c) defining a delayed signal by said predetermined amount of current and said discharging of said capacitance node; and
d) outputting, with an inverter device coupled to a drain of said current source FET, said delayed signal.
The present invention also provides a system having a programmable delay pulse generator comprising:
a programmable delay device for receiving an input signal, producing a predetermined amount of current and outputting a first delayed signal;
a signal lock-out delay element for receiving said input signal and outputting a second delayed signal;
a pulse trigger device, coupled to said programmable delay device and said signal lock-out delay element, for receiving said first and second delayed signal, wherein said second delayed signal prevents said pulse trigger device from receiving said first delayed signal within a predetermined time period;
an output device, coupled to said pulse trigger device, for receiving a pulse from said pulse trigger device and outputting a delayed signal; and
a reset device, coupled to said pulse trigger device and said output device, for resetting said pulse trigger device and said output device.
The present invention further provides a system having a data input, a first latch and a second latch, said system optimized to transfer said data input to said second latch in a minimum number of clock cycles, said system comprising:
a first clock;
a second clock; and
a programmable delay device, for delaying said first clock to latch said data input with said first latch within a predetermined amount of time and output a first latched data to said second latch, wherein said predetermined amount of time enables said first latched data to be latched with said second latch to coincide with a specific clock cycle of said second clock.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.